1. Field of the Invention
The present invention relates to a fabrication process for a MOS transistor, and a fabrication process for a CMOS transistor using the above process.
2. Description of Related Art
A surface channel type transistor is easily controlled by an electric field of a gate electrode because a current flows along the surface of a silicon substrate, and therefore, it is superior in switching characteristic to an embedded channel type transistor. In other words, the surface channel type transistor can reduce an OFF current as compared with the embedded channel type transistor. For this reason, to meet a requirement to reduce a current consumption, each of an Nch transistor and a Pch transistor has come to be of a surface channel type.
Incidentally, a CMOS transistor having an Nch transistor and a Pch transistor each of which is of a surface channel type, is generally fabricated in accordance with processing steps shown in FIGS. 1A to 1D and FIG. 2. FIGS. 1A to 1D are sectional views taken along the direction perpendicular to the length direction of a gate electrode, in which only one of an Nch transistor region and a Pch transistor region is illustrated; and FIG. 2 is a sectional view taken along the direction parallel to the length direction of the gate electrode.
The related art fabricating process for a CMOS transistor will be described with reference to FIGS. 1A to 1D and FIG. 2. As shown in FIG. 1A, element isolation regions 2 are formed on a silicon substrate 1 by LOCOS, to isolate an Nch transistor region (NchTr) from a Pch transistor (PchTr) as shown in FIG. 2. Next, as shown in FIG. 1A, a gate oxide film 3 is formed on the silicon substrate 1, and a Si film 4 made of crystalline or amorphous pure silicon (doped with no impurity) is deposited on the gate oxide film 2. Subsequently, an N-type impurity and a P-type impurity are doped on the NchTr side and the PchTr side shown in FIG. 2 by ion implantation respectively, to give the Si film 4 in each region a conductivity of a type corresponding to that of transistors to be formed in the region.
A film (not shown) made of tungsten silicide (WSi.sub.x) is formed on the Si film 4, followed by patterning of the film and Si film 4, to form gate electrodes 5 each having a polycide structure composed of a silicon portion 5a and a metal silicide portion 5b as shown in FIG. 1B. Then, an N-type impurity and a P-type impurity are doped on the NchTr side and the PchTr side by ion implantation using these gate electrodes 5 as a mask respectively, followed by activation of these impurities by heat treatment, to form LDD diffusion layers 6 corresponding to the transistors to be formed in each region as shown in FIG. 1C.
Next, side walls 7 are formed on both the sides of each gate electrode 5. An N-type impurity and a P-type impurity are doped on the NchTr side and PchTr side by ion implantation using the side walls 7 and the gate electrodes 5 as a mask respectively, followed by activation of these impurities thus doped by heat treatment, to form diffusion layers 8 as source/drain regions corresponding to the transistors to be formed in each region as shown in FIG. 1D.
Incidentally, in the above-described related art fabrication process for a CMOS transistor, as described above, to make lower the resistance of the gate electrode 5, and to electrically connect the gate electrodes 5 in the VchTr and the PchTr to each other, the gate electrode 5 is configured to be of the polycide structure composed of the silicon portion 5a and the metal silicide portion 5b.
Such a polycide structure of the gate electrode, however, presents a problem. That is, by the heat treatment performed to activate the doped impurities for forming the LDD diffusion layers 6 and the diffusion layers 8 after formation of the gate electrodes 5, the impurities in the silicon portions 5a of the gate electrodes 5 are easily mutually diffused through the metal silicide portions 5b as shown in FIG. 3, and such mutual diffusion of the impurities reduces the concentration of the impurity in the silicon portion 5a of each gate electrode 5, to change the work function of the gate electrode, thus rendering variable the threshold voltage of the transistor.